1. Field of the Invention
The present invention relates to an input protector device for a semiconductor device such as a CMOS device or the like.
2. Description of the Prior Art
In FIGS. 1 and 2, there is shown a conventional input protector device for a semiconductor device, for example, an n-channel complementary metal oxide semiconductor (CMOS) device having a P-type well region formed in the surface area of an N-type semiconductor substrate. As shown in FIG. 1, in an N-type semiconductor substrate 1, a P.sup.+ -type diffusion region 2, an N.sup.+ -type contact region 3 and two P-type well regions 4 and 5 are separately formed in its main surface area. A P.sup.+ -type well contact region 6 and an N.sup.+ -type region 7 are formed, respectively, in the right side border portion and the left side portion of the surface area of the P-type well region 4, and an N.sup.+ -type diffusion region 8 is formed in the surface area of the P-type well region 5. A polycrystalline silicon film 11 is formed as an electrode on the N.sup.+ -type diffusion region 8 via an insulating film 9. A silicon oxide insulating film 12 is formed over the main surface of the N-type semiconductor substrate 1.
In this embodiment, the P.sup.+ -type diffusion region 2 acts as a resistor 13, of which the left side end portion is coupled to an input terminal 14 and the right side end portion is connected to an output terminal 18 to be connected to a semiconductor device such as a CMOS device to be protected. The resistor 13 is designed to possess a resistance of approximately several hundreds of kiloohms and is cooperated with a capacitor 17 to constitute a filter circuit for a high frequency wave noise, as hereinafter described in detail. The PN junction of the P.sup.+ -type diffusion region 2 and the N-type substrate 1 constitutes a first diode 15, and its cathode is coupled to a power source V.sub.DD through the N.sup.+ -type contact region 3. The PN junction of the P-type well region 4 and the N.sup.+ -type region 7 constitutes a second diode 16, of which the cathode is connected to the right side end of the resistor 13 and the output terminal 18, and the anode is linked to a low voltage source V.sub.SS such as the ground or the like. The N.sup.+ -type diffusion region 8, the insulating film 9 and the polycrystalline silicon electrode 11 constitute the capacitor 17 by virtue of the electrostatic induction of its MOS structure. One end 8 of the capacitor 17 is connected to the low volyage source V.sub.SS, and the other end 11 of the same is connected to the right side end of the resistor 13. The capacitor 17 and the resistor 13 constitute a filter circuit, and its output terminal 18 is connected to the CMOS device (not shown) which is formed in another portion of the N-type substrate 1.
On a normal operation, a signal fed to the input terminal 14 is supplied to the CMOS through the resistor 13, while the first and second diodes 15 and 16 are reversely biased to be electrically separated from each other.
When a noise having a higher voltage than that of the power source V.sub.DD is given to the input terminal 14, the first diode 15 is foward-biased, and the noise is bypassed to the power source V.sub.DD through the N-type substrate 1. In turn, when a noise having a lower voltage than that of the low voltage source V.sub.SS is supplied to the input terminal 14, the second diode 16 is foward-biased to by-pass the noise to the low voltage source V.sub.SS via the P-type well region 4.
When a signal carrying a high frequency noise is fed to the input terminal 14, the filter circuit composed of the resistor 13 and the capacitor 17 is actuated to remove a noise having a shorter period than the time constant determined by the product of the resistor 13 and the capacitor 17, thereby preventing a malfunction. The high frequency noise which malfunctions the CMOS device usually possesses a frequency of approximately several MHz to several GHz, and the capacitance of the MOS capacitor actually admissible in the MOS device is several 10 pF. Accordingly, the resistance of the resistor 13 which is composed the filter circuit together with the capacitor 17 is determined to approximately several 100 kiloohms.
However, in the above described conventional device, since the resistor 13 having a relatively large resistance of several 100 kiloohms is formed by the P.sup.+ -type diffusion region 2, the length of the resistor pattern becomes long, and its chip area inevitably becomes large, which brings about the cost increase.
Then, in order to remove the problem of the first conventional device, another conventional input protector device has been developed, in which a resistor is formed using a high resistance diffusion area such as P-type well region, as shown in FIG. 3. In the drawing, a P-type well region 22 is formed in the surface area of the N-type substrate 1, and a pair of P.sup.+ -type well contact regions 21a and 21b are formed in the left and right side end portions of the surface area of the P-type well region 22. In this embodiment, the resistor 13 is formed by the high resistance diffusion area of the P-type well region 22, and the PN junction of the P-type well region 22 and the N-type substrate 1 constitutes the first diode 15.
In this case, the resistance of the P-type well region 22 increases approximately 1000 times as high as that of the P.sup.+ -type diffusion region 2 in FIG. 1, and therefore, when the resistor having the resistance of several 100 kiloohms is formed in the P-type well region, the pattern area and thus its chip area can be largely reduced in comparison with those formed in the P.sup.+ -type diffusion region, with the result of saving the manufacturing cost.
However, in the first and second conventional devices, the following problem arises. That is, as described above, when the noise having the higher voltage than that of the power source V.sub.DD is fed to the input terminal 14, the first diode 15 composed of the PN junction of the P.sup.+ -type diffusion region 2 or the P-type well region 22 and the N-type substrate 1 is foward-biased, the noise is by-passed to the power source V.sub.DD via the N-type substrate 1. On this occasion, a large number of holes (the minority carrier) are injected from the P.sup.+ -type diffusion region 2 or the P-type well region 22 into the N-type substrate 1. The injected holes spread in the N-type substrate 1 to reach another P-type well region and may bring about a voltage change of the P-type well region, that is, may turn on a parasitic bipolar transistor or a parasitic thyristor, i.e., act as a trigger on a undesirable latchup phenomenon.
In order to avoid the latchup phenomenon, it is necessary to control the actuation of the parasitic bipolar transistor or the parasitic thyristor by, for instance, providing the P.sup.+ -type diffusion region 2 or the P-type well region 22 in the position sufficiently apart from the semiconductor device such as the CMOS or the like. However, in such a case, the chip area further increases in the first conventional device, and it is difficult to reduce the chip area even when the resistor 13 is formed using the high resistance diffusion area of the P-type well region 22 in the second conventional device.
Furthermore, in order to remove the above problem, a still another conventional input protector device has been proposed, as shown in FIG. 4, in which an N.sup.- -type polycrystalline silicon layer 32 having a high resistance is formed as the resistor 13 on a silicon oxide film 12 of the N-type semiconductor substrate 1, and the polycrystalline silicon 32 is provided with a pair of contact regions 31a and 31b of N.sup.+ -type polycrystalline silicon in the left and right side ends. In this embodiment, the first diode is independently formed in the N-type substrate 1 and is to be connected to the resistor 13 of the polycrystalline silicon 32.
In this case, the injection of the holes from the resistor 13 into the N-type substrate 1 can be prevented, and the resistor 13 having several 100 kiloohms can be formed using the polycrystalline silicon 32 of the high resistance, with a small pattern area thereof. When the noise having the higher voltage than that of the power source V.sub.DD is supplied to the input terminal 14, the holes are injected from the first diode positioned in the followed stage of the resistor 13 to the N-type substrate 1. However, in this embodiment, the current is restricted by the resistor 13 of the polycrystalline silicon 32, and hence the amount of the injected holes is so limited to the low level that the latchup may not be caused.
However, in the third conventional device, a doping step of an impurity such as ions into the polycrystalline silicon for controlling the resistance of the resistor 13 is required, which brings about the cost increase due to the increase of the number of the steps. Further, as compared with the second conventional device including the resistor 13 formed using the P-type well region of the high resistance diffusion area, the dispersion of the resistance values of the resistor 13 becomes large and it is difficult to control the accuracy of the resistance value.